The present invention relates generally to microlithography. More particularly, the present invention is directed towards improving alignment and overlay during the patterning of substrates.
Microlithography is used in the formation of integrated circuits which may require transfer of multiple layers of patterns onto a substrate, superimposed upon on another. As a result, transfer of patterns onto substrates is an important process in the fabrication of integrated circuits. Pattern transfer techniques are also used in optical technology, biotechnology, and the like. A common technique for patterning of substrates is an optical lithography process known as photolithography. An original pattern, referred to as a master pattern, is stored on photomasks. Photomasks are typically fused silica plates with a pattern recorded therein employing a high-precision laser or an electron beam. Photomask patterns are transferred onto a photo-sensitive resist material coated on top of the substrate undergoing processing. The substrate is then etched and the transferred patterns are used to control the etch process so that a desired pattern may be created in the substrate. A differing patterning process, in which the topography of a mold defines the pattern transferred onto a substrate, is known as imprint lithography.
In either of the aforementioned patterning processes the dimension of the smallest feature in the pattern, called the critical dimension (CD) may be maintained to within 10 nm. As a result, a successful transfer of a pattern onto the substrate requires precise positioning with respect to the features of an existing pattern on the substrate. A general rule of thumb states that for a pattern layer to be functional, every point on the pattern must be aligned to every point on the underlying pattern to within ⅓rd of the CD in the pattern. Overlay requirements for various technology nodes are available from International Technology Roadmap for Semiconductors, at http://public.itrs.net. The process by which to properly position the transferred patterns is referred to as alignment. By achieving proper alignment, desired pattern overlay is achieved. Specifically, alignment accuracy is measured at the position of a few alignment marks. This accuracy is a measure of the precision in the patterning tool's alignment system.
Overlay accuracy, which is a measure of the alignment of each point in the pattern, is measured everywhere in a field to be patterned in addition to the location of the alignment marks. As a result, overlay information may include error information in addition to the error information associated with alignment information. For example, overlay error may result from lens distortions, chuck-induced wafer distortion, and image placement errors on the mask/mold, referred to collectively as pattern device, which may cause significant overlay errors, despite accurate alignment. These errors may result in distortions in transferred patterns that may substantially reduce production yield. Pattern to pattern overlay errors are typically quantified by measuring the alignment over a grid of points in a field. Prior art attempts have been made to attenuate alignment errors at the site of the alignment marks.
In U.S. Pat. No. 6,847,433 to White et al. disclose a deformable holder, system, and process where long range errors (any of lithography, metrology, or overlay errors) between the image of a mask and an existing pattern on a wafer from a number of potential sources are corrected. The long range errors are determined using either a through-the-lens alignment metrology system or an around-the-lens metrology system. Deformation values are determined to compensate for the long range errors. The deformation values are determined by either solving simultaneous equations or by finite-element linear-stress-analysis (FEA). The mask or wafer is then distorted, in-plane, by an amount related to the determined deformation values using an actuator such a piezoelectric ceramic to push or pull the mask or wafer to substantially realign the projected image of the mask and the existing pattern on the wafer. This approach guarantees alignment at the site of the alignment marks and not necessarily overlay over the entire field. Another drawback with this and other prior art attempts at minimizing pattern distortions concerns the computational requirements to determine deformation values, especially if these types of corrections are to be done real-time with time constraints. Typically, determination of deformation values requires a great amount of computational power that may increase the cost of a system and is often inaccurate.
What is needed, therefore, is an improved system and technique to correct alignment and overlay errors and to compute deformation values.